1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a programming method for a nonvolatile memory apparatus.
2. Related Art
In a nonvolatile memory apparatus represented by a flash memory apparatus, a data level stored in each memory cell is defined by a threshold voltage of the memory cell, and a program operation is performed by a method of changing the threshold voltage of the memory cell.
In general, a program operation of a nonvolatile memory apparatus is performed by an incremental step pulse program (ISSP) scheme, and will be described below with reference to FIG. 1.
An active high signal is said to be asserted when it is in the high level, and an active low signal is said to be asserted when it is in the low level. Additionally, when referring to signals, the terms “asserted,” and “enabled” may be used interchangeably depending upon context. Similarly, the terms “deasserted” and “disabled” may be used interchangeably depending upon context.
FIG. 1 is a diagram explaining a program method using the ISSP scheme.
First, a first-step program pulse VPGM1 is applied to program selected memory cells. Then, a verification voltage PVER is applied to the selected memory cells so as to pass memory cells with threshold voltages Vth1 higher than the verification voltage PVER.
After that, a second-step program pulse VPGM2, which has an increase of a constant voltage over the first step-program pulse Vth1, is applied to program the memory cells with threshold voltages Vth2 equal to or lower than the verification voltage PVER. At this time, the passed memory cells with the threshold voltages Vth1 are not programmed, thereby preventing the memory cells from being over-programmed.
Similarly, even after the second-step program pulse VPGM2 is applied to perform the program, the threshold voltages Vth3 and Vth4 of the memory cells are compared with the verification voltage VPER, and the program and the verification are performed while gradually increasing the program pulse (VPGM3, VPGM4, . . . ) until all the memory cells are programmed.
That is, referring to FIG. 2, the program pulse voltage is increased in steps as the threshold value Vth of certain memory cells selected for programming become increasingly higher than the verification voltage PVER.
Recently, a double verification method has been used during a program operation, in order to make more uniform the threshold voltage distribution of programmed cells.
In the double verification method, the level of a program pulse differs depending on the threshold voltage levels of selected cells. In a verification process, cells having a threshold voltage Vth higher than a verification voltage are classified into program-prohibited cells, cells having a threshold voltages Vth lower than the verification voltage but higher than a preset reference voltage are classified into low-speed program cells, and cells having a threshold voltages Vth lower than the preset reference voltage are classified into general program cells.
After the cells are classified in such a manner, a subsequent program pulse is not applied to the program-prohibited cells. Meanwhile, a low-speed program pulse is applied to the low-speed program cells, and a normal program pulse is applied to the general program cells, as in a general ISSP scheme.
For this process, an operation of setting up a bit line depending on the threshold voltages of cells to be programmed should be done before the program pulses are applied.
FIG. 3 is a diagram explaining a conventional bit line setup method in a nonvolatile memory apparatus, and shows a case in which an even bit line BLe is programmed.
When the even bit line BLe is to be programmed, an odd bit line BLo should be in a program-prohibited state. For this condition, an even discharge signal DISCHE and an odd discharge signal DISCHO are enabled, and a power supply voltage VCC is applied to a verification voltage application terminal VIRPWR to precharge the even bit line BLe and the odd bit line BLo ({circle around (1)}).
Subsequently, in order to discharge a bit line coupled to a memory cell to be programmed, that is, the even bit line BLe, the even discharge signal DISCHE is disabled, and an even bit line selection signal SELBLE is enabled. Furthermore, the odd discharge signal DISCHO maintains the enable state, and an odd bit line selection signal SELBLO is disabled.
At this time, a first latch SL1 of a page buffer coupled to a memory cell which has been programmed stores high-level data such that the memory cell is not over-programmed. As a sensing control signal PBSENSE and a main data transmission signal MTRAN are enabled, a discharge operation does not occur in a bit line coupled to the memory cell which has been completely programmed. On the other hand, since the first latch SL1 of a page buffer coupled to the memory cell classified as a general program cell stores low-level data, a discharge operation occurs ({circle around (2)}).
Then, in order that a bit line coupled to a low-speed program cell has a preset level Va (<VCC), a temporary data transmission signal TTRAN is enabled. At this time, the sum Vth+Va of a threshold voltage of a transistor N4 to which the temporary data transmission signal TTRAN is applied and the preset level of voltage is applied ({circle around (3)}).
Through the above-described process, the bit line voltage of the program-prohibited cell becomes a power supply voltage (VCC) level, the bit line voltage of the low-speed program cell becomes the preset voltage (Va) level, and the voltage of the general program cell becomes a logic low level.
FIG. 4 is a graph explaining changes in the bit line voltage during the bit line setup.
While the even bit line BLe and the odd bit line BLo are precharged ({circle around (1)}), the voltage V_BL of the even bit line BLe gradually increases to the power supply voltage level.
While the even bit line BLe is discharged ({circle around (2)}), the bit line voltage V_BL of the program-prohibited cell which has been already programmed maintains the power supply voltage level, and the bit line voltage V_BL of the general program cell is discharged to a low level.
Furthermore, while the bit line coupled to the low-speed program cell is set up ({circle around (3)}), the bit line voltage V_BL of the program-prohibited cell maintains the power supply voltage level, the bit line voltage V_BL of the general program cell maintains a low level, and the bit line voltage V_BL of the low-speed program cell changes to the preset level Va.
In FIG. 4, ‘11’ represents a data value stored in the first and second latches SL1 and SL2 when the bit line of the program-prohibited cell is set up, ‘00’ represents a data value stored in the first and second latches SL1 and SL2 when the bit line of the general program cell is set up, and ‘01’ represents a data value stored in the first and second latches SL1 and SL2 when the bit line of the low-speed program cell is set up.
As such, since the process of setting up the bit line for the program operation in the nonvolatile memory apparatus is performed in three stages, a considerable amount of time is required for the setup process.
Furthermore, after a bit line of a memory cell to be programmed should be precharged, the bit line should be discharged, and the discharged bit line should be again precharged to the preset level Va. Therefore, the current consumption increases. Furthermore, when the precharged bit line is again discharged, a coupling capacitance with an adjacent bit line may occur. In this case, the voltage of the bit line which should maintain the precharge state may be reduced, and thus current consumption may occur to compensate this reduction. Furthermore, when a voltage is supplied to maintain the precharge voltage, a peak current may flow. In this case, a sudden voltage drop may occur, and thus a system clock down may occur.